The present invention relates to determining the accumulated thermal and or vibration fatigue stress fatigue of an electronic system, and more particularly to a mirrored continuity circuit to determine the accumulated printed wiring board fatigue damage.
During its design life, an electronic system can be exposed to a wide variety of vibration and thermal cycling environments. In order to reduce testing time and cost, laboratory tests are usually conducted on products in a time-accelerated manner to create a generalized analytic model that is applied to average or generalized anticipated operating conditions to predict service life of products.
Integrated circuit (IC) chips are often soldered to conductor patterns formed on a circuit board, which may be a ceramic substrate or printed wiring board, in a manner which both secures and electrically interconnects the IC chip to the circuit board. Terminals are formed on the lower surface of the IC chip such that, when the chip is registered with the conductor pattern, each terminal will individually register with a single conductor of the conductor pattern. A solder reflow technique is then typically used to reflow the terminals and metallurgically bond them to their respective conductors.
Due to the numerous functions performed by integrated circuits, a relatively large number of terminals are required to interconnect the IC chip to the conductor pattern. Furthermore, because the size of an IC chip can be as little as a few millimeters per side, the size and spacing of the terminals and the conductors must be closely controlled in order to properly align and mount an IC chip to the corresponding terminal pattern formed on its circuit board.
A method which is widely practiced by the industry for soldering IC chips to a substrate is the flip-chip bonding process. This process utilizes an integrated circuit flip chip, which is generally a monolithic semiconductor device having bead-like terminals, or solder bumps, provided on one face of the chip. The solder bumps form a bump pattern and serve as interconnects between the IC chip and its corresponding conductor pattern on the substrate to which the flip chip is to be soldered by reflowing the solder bumps.
In the field of integrated circuits packaging, a ball grid array package (BGA package) is a common type utilized in ICs packaging in which the plurality of bumps form the BGA in a flip chip fashion. As an example, a conventional flip chip bump pattern composed of eighty-eight solder bumps arranged as a rectangular array with a row of twenty-two solder bumps to a side, with each row being adjacent an edge of the flip chip. In order to properly register with the single row, rectangular arrangement of this particular bump pattern, the individual conductors of this flip chip's conductor pattern are also so spaced. Because of the close placement of the solder bumps and conductors, the techniques used to pattern the bump and conductor patterns on the surface of the flip chip and to solder the flip chip to its conductor pattern require a significant degree of precision. The size and composition of the solder bumps must also be closely controlled to achieve the required reliability, bond integrity and electrical characteristics, while concurrently eliminating the potential for electrical shorting between adjacent solder bumps and adjacent conductors.
While presently known techniques used to form the terminal and conductor patterns for flip chip and ball grid array packages are generally sufficient, electronic systems are complex structures with characteristics that may make accurate predictive analysis quite difficult. One area of concern is the fatigue life of the solder joints formed by the terminals with the conductors, and more specifically, the stress induced in the solder joints as a result of temperature effects and differences in coefficients of thermal expansion of the materials used.
Further complicating predictive analysis is that the life-environment actually experienced by each particular electronic system is unique. Such individuality is particularly prevalent in the vibration-fatigue life of military and commercial avionic systems. Predictive analysis, although effective, may not define the risk for all possible failures for individual systems which may result in unnecessary anticipatory preventative maintenance and repair which may increase the associated life cycle costs, or inability to predict imminent failure which can create economic or human costs when failure occurs.
Accordingly, it is desirable to provide an in-situ monitoring system and method to determine if an individual electronic system is near the end of a thermal or vibration-fatigue life based on the life-environment actually experienced.